1. Field of the Invention
This invention relates to the field of digital information processing systems. More particularly, this invention relates to microarchitecture hardware implementation in connection with certain mathematical algorithms for improving the computing capacity of such systems.
2. Art Background
A common method of improving speed of a computer system is to employ a math processor, separate from the main processor, for performing mathematical calculations. The combination main processor and math processor provides greatly increased speed of system operation, since math processors are optimized for performing mathematical calculations, and since the burden of performing specialized calculations is lifted from the main processor. Tasks typically delegated to a math processor include addition, subtraction, multiplication and division. To save critical space within the math processor, many component circuits of the math processor are designed to perform several functions. For example, it is quite common for the same component circuits to be used when performing multiplication, division and square root functions.
Each new generation of computer system design requires increasingly sophisticated computers to perform calculations faster than previous generations of computers and to perform the calculations with increasingly greater precision. Previous math processors used single digit, or 1 bit of quotient per clock (radix 2), nonrestoring division steps to generate the division function. However, this method is time-consuming since the number of division steps required increases approximately proportionally to the precision required for the division operation. The large number of steps required by single digit nonrestoring division, particularly for IEEE floating point extended precision, greatly slows the division function.
Furthermore, in slower divider circuits, or in divider circuits which do not have a wide data path width required by extended precision, when a lesser precision result is required than the maximum precision of the divider, it is common to permit the significant bits of the quotient to accumulate in a format such that the most significant bits (MSBs) of the quotient occupy the least significant bits (LSBs) which are output from the divider. A steering multiplexer (MUX) is then placed between the divider circuit and the result bus and is used to steer the significant bits to their proper position on the bus (i.e. so that the significant bits of the quotient occupy the most significant bits of the result bus regardless of the precision specified for the division operation). Generally, no shifting is required by the steering MUX for the maximum precision case, because a maximum result has the same number of significant bits as the width of the result bus.
However, in the worst case, (i.e. a single precision divide with an extended precision result bus), the significant bits of the resulting quotient would have to be shifted to a higher order by 40 bit positions and the least significant 40 bits filled with zeros. The use of a steering MUX following the divider circuit is not practical in a fast, extended precision processor for several reasons. First, the paths necessary to perform a 40 bit position shift for a single precision result, and a 12 bit position shift for an extended precision result, would occupy an unacceptably large amount of critical area upon the circuit board. Also, the length and number of the traces to perform the shifts would place a large capacitive load upon the final stage of the divider circuit.
Furthermore, if a steering MUX were used between the final stage of the divider circuit and the result bus, additional logic would be required there to implement the MUX. The increased logic would increase the load which the final stage must drive, thereby requiring that a larger driver be used in the final stage. A larger driver in the final stage would increase the area of the final stage, as well as its power consumption. Additionally, the increased amount of logic in the steering MUX would occupy additional precious board area and would introduce additional propagation delay. The latter is significant since the steering MUX would lie upon the critical path of the divider if it were coupled between the output of the final stage and the result bus.
As will be disclosed, the present invention provides a method and apparatus for improving the speed of the division function by implementing non critical path significant bit position correction steering logic thereby decreasing the time spent by the division circuitry to generate a quotient with a selected single, double or extended precision.